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1 industrial temperature range idt5t9955 2.5v programmable skew dual pll clock driver turboclock w june 2002 2002 integrated device technology, inc. dsc 5976/10 c industrial temperature range the idt logo is a registered trademark of integrated device technology, inc. features: ? ref input is 3.3v tolerant ? 8 pairs of programmable skew outputs ? low skew: 185ps same pair, 250ps same bank, 350ps both banks ? selectable positive or negative edge synchronization on each bank: excellent for dsp applications ? synchronous output enable on each bank ? input frequency: 2mhz to 160mhz ? output frequency: 6mhz to 160mhz ? 3-level inputs for skew and pll range control ? 3-level inputs for feedback divide selection multiply / divide ratios of (1-6, 8, 10, 12) / (2, 4) ? pll bypass for dc testing ? external feedback, internal loop filter ? 12ma balanced drive outputs ? low jitter: <100ps cycle-to-cycle ? power-down mode on each bank ? lock indicator on each bank ? available in bga package functional block diagram b fs b pe b lock pll 3 bsoe / n 3 3 b fb 3 3 skew select skew select skew select skew select 3 3 3 3 3 3 b1q 0 b1q 1 b1f1:0 b2q 0 b2q 1 b2f1:0 bds1:0 b3q 0 b3q 1 b3f1:0 b4q 0 b4q 1 b4f1:0 bpd 3 a fs a pe a lock pll 3 a soe ref / n 3 3 a fb 3 3 skew select 3 3 3 3 3 3 a1q 0 a1q 1 a1f1:0 a2q 0 a2q 1 a2f1:0 ads1:0 a3q 0 a3q 1 a3f1:0 a4q 0 a4q 1 a4f1:0 apd test 3 skew select skew select skew select idt5t9955 2.5v programmable skew dual pll clock driver turboclock? w description: the idt5t9955 is a high fanout 2.5v pll based clock driver intended for high performance computing and data-communications applications. a key feature of the programmable skew is the ability of outputs to lead or lag the ref input signal. the idt5t9955 has sixteen programmable skew outputs in eight banks of 2. the two separate plls allow the user to independently control a and b banks. skew is controlled by 3-level input signals that may be hard-wired to appropriate high-mid-low levels. the feedback input allows divide-by-functionality from 1 to 12 through the use of the xds[1:0] inputs. this provides the user with frequency multiplication from 1 to 12 without using divided outputs for feedback. when the x soe pin is held low, all the xbank outputs are synchronously enabled. however, if x soe is held high, all the xbank outputs except x2q0 and x2q1 are synchronously disabled. the xlock output is high when the xbank pll has achieved phase lock. furthermore, when xpe is held high, all the outputs are synchronized with the positive edge of the ref clock input. when xpe is held low, all the outputs are synchronized with the negative edge of ref. the idt5t9955 has lvttl outputs with 12ma balanced drive outputs.
2 industrial temperature range idt5t9955 2.5v programmable skew dual pll clock driver turboclock w pin configuration 96 ball fpbga package attributes a bc e f gh j klmnp d r t 6 5 4 3 2 1 a3q 1 a3q 0 agnd afb a2q 1 a2q 0 a4q 0 agnd agnd agnd agnd a1q 1 a pe agnd av ddq a pd a s oe av ddq av ddq ads0 a lock a4f 1 a4f 0 a1f 0 ads 1 afs av dd av ddq ref agnd a2f 1 b2f 1 test bgnd a4q 1 agnd agnd agnd agnd a1q 0 av ddq av ddq av ddq av ddq av ddq a3f 1 a3f 0 a2f 0 a1f 1 av ddq av ddq bv ddq bv dd bfs b1f 1 b2f 0 bv ddq bv ddq b3f 0 b3f 1 bds 1 b1f 0 b4f 0 b4f 1 bv ddq bv ddq bv ddq bv ddq bv ddq bv ddq bgnd bgnd bgnd bgnd bfb bgnd bgnd bgnd bgnd b lock bds 0 b s oe b pd bv ddq bv ddq b pe b1q 0 b4q 1 bgnd bgnd b1q 1 b4q 0 b2q 0 b2q 1 b3q 0 b3q 1 fpbga top view 1.5mm max. 1.4mm nom. 1.3mm min. 0.8mm 6 5 4 3 2 1 top view abcdefghjklmnprt abcdefghjklmnprt 6 5 4 3 2 1 13.5mm 5.5mm
3 industrial temperature range idt5t9955 2.5v programmable skew dual pll clock driver turboclock w note: 1. capacitance applies to all inputs except test, xfs, xnf [1:0] , and xds [1:0] . capacitance (t a = +25c, f = 1mhz, v in = 0v) parameter description typ. max. unit c in input capacitance ref 8 10 pf others 5 7 note: 1. stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute- maximum-rated conditions for extended periods may affect device reliability. absolute maximum ratings (1) symbol description max unit v ddq , v dd supply voltage to ground ?0.5 to +4.6 v v i dc input voltage ?0.5 to v dd +0.5 v ref input voltage ?0.5 to +4.6 v maximum power t a = 85c 1.1 w dissipation t a = 55c 1.9 t stg storage temperature range ?65 to +150 c note: 1. when test = mid and x soe = high, pll remains active with xnf[ 1:0 ] = ll functioning as an output disable control for individual output banks. skew selections remain in effect unless xnf[ 1:0 ] = ll. pin description pin name type description ref i n reference clock input xfb i n individual feedback inputs for a and b banks test (1) i n when mid or high, disables pll for a and b banks (except for conditions of note 1). ref goes to all outputs. skew selection s (see control summary table) remain in effect. set low for normal operation. x soe (1) i n individual synchronous output enable for a and b banks. when high, it stops clock outputs (except x2q 0 and x2q 1 ) in a low state (for xpe = h) - x2q 0 and x2q 1 may be used as the feedback signal to maintain phase lock. when test is held at mid level and x soe is high, the nf[ 1:0 ] pins act as output disable controls for individual banks when xnf[ 1:0 ] = ll. set x soe low for normal operation (has internal pull-down). xpe i n individual selectable positive or negative edge control for a and b banks. when low/high the outputs are synchronized wit h the negative/ positive edge of the reference clock (has internal pull-up). xnf [1:0] i n 3-level inputs for selecting 1 of 9 skew taps or frequency functions xfs i n selects appropriate oscillator circuit based on anticipated frequency range. (see programmable skew range.) individual c ontrol on a and b banks. xnq [1:0] out eight banks of two outputs with programmable skew xds [1:0] i n 3-level inputs for feedback divider selection for a and b banks x pd i n power down control. shuts off either a or b bank of the chip when low (has internal pull-up). xlock out pll lock indication signal for a and b banks. high indicates lock. low indicates that the pll is not locked and outputs may n ot be synchronized to the inputs. v ddq pwr power supply for output buffers v dd pwr power supply for phase locked loop, lock output, and other internal circuitry gnd pwr ground
4 industrial temperature range idt5t9955 2.5v programmable skew dual pll clock driver turboclock w output skew with respect to the ref input is adjustable to compensate for pcb trace delays, backplane propagation delays or to accommodate requirements for special timing relationships between clocked compo- nents. skew is selectable as a multiple of a time unit (t u ) which ranges from 782ps to 1.5625ns (see programmable skew range and resolu- tion table). there are nine skew configurations available for each out- put pair. these configurations are chosen by the xnf 1:0 control pins. in order to minimize the number of control pins, 3-level inputs (high-mid- low) are used, they are intended for but not restricted to hard-wiring. undriven 3-level inputs default to the mid level. where programmable skew is not a requirement, the control pins can be left open for the zero skew default setting. the control summary table shows how to select specific skew taps by using the xnf 1:0 control pins. programmable skew external feedback by providing two separate external feedbacks, the idt5t9955 gives users flexibility with regard to skew adjustment. the xfb signal is com- pared with the input ref signal at the phase detector in order to drive the vco. phase differences cause the vco of the pll to adjust up- wards or downwards accordingly. notes: 1. the device may be operated outside recommended frequency ranges without damage, but functional operation is not guaranteed. 2. the level to be set on xfs is determined by the nominal operating frequency of the vco and time unit generator. the vco frequ ency always appears at x1q 1:0 , x2q 1:0 , and the higher outputs when they are operated in their undivided modes. the frequency appearing at the ref and xfb inputs will be f nom when the output connected to xfb is undivided and xds[ 1:0 ] = mm. the frequency of the ref and xfb inputs will be f nom /2 or f nom /4 when the part is configured for frequency multiplication by using a divided output as the xfb input and setting xds[ 1:0 ] = mm. using the xds[ 1:0 ] inputs allows a different method for frequency multiplication (see divide selection table). 3. skew adjustment range assumes that a zero skew output is used for feedback. if a skewed xq output is used for feedback, then adjustment range will be greater. for example if a 4t u skewed output is used for feedback, all other outputs will be skewed ?4t u in addition to whatever skew value is programmed for those outputs. ?max adjustment? range applies to output pairs 3 and 4 where 6t u skew adjustment is possible and at the lowest f nom value. an internal loop filter moderates the response of the vco to the phase detector. the loop filter transfer function has been chosen to provide minimal jitter (or frequency variation) while still providing accu- rate responses to input frequency changes. xfs = low xfs = mid xfs = high comments timing unit calculation (t u ) 1/(32 x f nom ) 1/(16 x f nom ) 1/(8 x f nom ) vco frequency range (f nom ) (1,2) 24 to 40mhz 40 to 80mhz 80 to 160mhz skew adjustment range (3) max adjustment: 7.8125ns 9.375ns 9.375ns ns 67.5 135 270 phase degrees 18.75% 37.5% 75% % of cycle time example 1, f nom = 25mhz t u = 1.25ns ? ? example 2, f nom = 37.5mhz t u = 0.833ns ? ? example 3, f nom = 50mhz ? t u = 1.25ns ? example 4, f nom = 75mhz ? t u = 0.833ns ? example 5, f nom = 100mhz ? ? t u = 1.25ns example 6, f nom = 150mhz ? ? t u = 0.833ns programmable skew range and resolution table
5 industrial temperature range idt5t9955 2.5v programmable skew dual pll clock driver turboclock w divide selection table xds [ 1:0 ] xfb divide-by-n permitted output divide-by-n connected to xfb in (1) ll 2 1 or 2 lm 3 1 lh 4 1, 2, or 4 ml 5 1 or 2 m m 1 1, 2, or 4 m h 6 1 or 2 hl 8 1 or 2 hm 10 1 hh 12 1 note: 1. permissible output division ratios connected to xfb. the frequency of the ref input will be f nom /n when the part is configured for frequency multiplication by using an undivided output for xfb and setting xds[ 1:0 ] to n (n = 1-6, 8, 10, 12). control summary table for feedback signals xnf1:0 skew (pair #1, #2) skew (pair #3) skew (pair #4) ll (1) ?4t u divide by 2 divide by 2 lm ?3t u ?6t u ?6t u lh ?2t u ?4t u ?4t u ml ?1t u ?2t u ?2t u m m zero skew zero skew zero skew mh 1t u 2t u 2t u hl 2t u 4t u 4t u hm 3t u 6t u 6t u hh 4t u divide by 4 inverted (2) notes: 1. ll disables outputs if test = mid and x soe = high. 2. when pair #4 is set to hh (inverted), x soe disables pair #4 high when xpe = high, x soe disables pair #4 low when xpe = low. recommended operating range symbol description min. typ. max. unit v dd /v ddq power supply voltage 2.3 2.5 2.7 v t a ambient operating temperature -40 +25 +85 c
6 industrial temperature range idt5t9955 2.5v programmable skew dual pll clock driver turboclock w dc electrical characteristics over operating range symbol parameter conditions (1) min. max. unit v ih input high voltage guaranteed logic high (ref, xfb inputs only) 2 ? v v il input low voltage guaranteed logic low (ref, xfb inputs only) ? 0.7 v v ihh input high voltage (2) 3-level inputs only v dd ? 0.4 ? v v imm input mid voltage (2) 3-level inputs only v dd /2 ? 0.2 v dd /2+0.2 v v ill input low voltage (2) 3-level inputs only ? 0.4 v i in input leakage current v in = v dd or gnd ? 5+5a (ref, xfb inputs only) v dd = max. v in = v dd high level ? +400 i 3 3-level input dc current v in = v dd /2 mid level ? 100 +100 a (test, xfs, xnf [1:0] , xds [1:0] )v in = gnd low level ? 400 ? i pu input pull-up current (xpe, x pd )v dd = max., v in = gnd ? 25 ? a i pd input pull-down current (x soe )v dd = max., v in = v dd ? +100 a v oh output high voltage v dd = min., i oh = ? 2ma (xlock output) 2 ? v v ddq = min., i oh = ? 12ma (xnq [1:0] outputs) 2 ? v ol output low voltage v dd = min., i ol = 2ma (xlock output) ? 0.4 v v ddq = min., i ol = 12ma (xnq [1:0] outputs) ? 0.4 notes: 1. all conditions apply to a and b banks. 2. these inputs are normally wired to v dd , gnd, or unconnected. internal termination resistors bias unconnected inputs to v dd /2. if these inputs are switched, the function and timing of the outputs may be glitched, and the pll may require an additional t lock time before all datasheet limits are achieved. notes: 1. measurements are for divide-by-1 outputs, xnf [1:0] = mm, and xds [1:0] = mm. all conditions apply to a and b banks. 2. for nominal voltage and temperature. power supply characteristics symbol parameter test conditions (1) typ. (2) max. unit i ddq quiescent power supply current v dd = max., test = mid, ref = low, 40 60 ma xpe = low, x soe = low, x pd = high fs = mid, all outputs unloaded i ddpd power down current v dd = max., x pd = low, x soe = low ? 50 a xpe = high, test = high, xfs = high xnf [1:0] = hh, xds [1:0] = hh ? i dd power supply current per input high v in = 2.3v, v dd = max., x pd = low 1 60 a (ref and xfb inputs only) test = high xfs = l 190 290 i ddd dynamic power supply current per output xfs = m 150 230 a/mhz xfs = h 130 200 xfs = l f vco = 40mhz, c l = 0pf 98 ? i tot total power supply current xfs = m f vco = 80mhz, c l = 0pf 132 ? ma xfs = h f vco = 160mhz, c l = 0pf 206 ?
7 industrial temperature range idt5t9955 2.5v programmable skew dual pll clock driver turboclock w input timing requirements symbol description (1) min. max. unit t r , t f maximum input rise and fall times, 0.7v to 1.7v ? 10 ns/v t pwc input clock pulse, high or low 2 ? ns d h input duty cycle 10 90 % xfs = low 2 40 f ref reference clock input frequency xfs = mid 3.33 80 m h z xfs = high 6.67 160 note: 1. where pulse width implied by d h is less than t pwc limit, t pwc limit applies.
8 industrial temperature range idt5t9955 2.5v programmable skew dual pll clock driver turboclock w switching characteristics over operating range symbol parameter min. typ. max. unit f nom vco frequency range see programmable skew range and resolution table t rpwh ref pulse width high (1) 2??ns t rpwl ref pulse width low (1) 2??ns t u programmable skew time unit see control summary table t skewpr zero output matched-pair skew (xnq 0 , xnq 1 ) (2,3) ? 50 185 ps t skew0 zero output skew (all outputs) (4) ? 0.1 0.25 ns t skewb bank skew (5) ? 0.1 0.35 ns t skew1 output skew (rise-rise, fall-fall, same class outputs) (6) ? 0.1 0.25 ns t skew2 output skew (rise-fall, nominal-inverted, divided-divided) (6) ? 0.2 0.5 ns t skew3 output skew (rise-rise, fall-fall, different class outputs) (6) ? 0.15 0.5 ns t skew4 output skew (rise-fall, nominal-divided, divided-inverted) (2) ? 0.3 0.9 ns t dev device-to-device skew (2,7) ? ? 0.75 ns t ( )1-3 static phase offset (xfs = l, m, h) (fb divide-by-n = 1, 2, 3) (8) ? 0.3 ? 0.3 ns t ( )h static phase offset (xfs = h) (7) ? 0.5 ? 0.5 ns t ( )m static phase offset (xfs = m) (7) ? 0.7 ? 0.7 ns t ( )l1-6 static phase offset (xfs = l) (xfb divide-by-n = 1, 2, 3, 4, 5, 6) (8) ? 0.7 ? 0.7 ns t ( )l8-12 static phase offset (xfs = l) (xfb divide-by-n = 8, 10, 12) (8) ? 1?1 ns t odcv output duty cycle variation from 50% ? 1?1 ns t pwh output high time deviation from 50% (9) ? ? 1.5 ns t pwl output low time deviation from 50% (10) ??2 ns t orise output rise time 0.15 0.7 1.5 ns t ofall output fall time 0.15 0.7 1.5 ns t lock pll lock time (11,12) ? ? 0.5 ms t ccjh cycle-to-cycle output jitter (peak-to-peak) ? ? 100 (divide by 1 output frequency, xfs = h, xfb divide-by-n=1,2) t ccjha cycle-to-cycle output jitter (peak-to-peak) ? ? 150 (divide by 1 output frequency, xfs = h, xfb divide-by-n=any) t ccjm cycle-to-cycle output jitter (peak-to-peak) ? ? 200 ps (divide by 1 output frequency, xfs = m) t ccjl cycle-to-cycle output jitter (peak-to-peak) ? ? 200 (divide by 1 output frequency, xfs = l, f ref > 3mhz) t ccjla cycle-to-cycle output jitter (peak-to-peak) ? ? 300 (divide by 1 output frequency, xfs = l, f ref < 3mhz) notes: 1. refer to input timing requirements table for more detail. 2. skew is the time between the earliest and the latest output transition among all outputs for which the same t u delay has been selected when all are loaded with the specified load. 3. t skewpr is the skew between a pair of outputs (xnq0 and xnq1) when all sixteen outputs are selected for 0t u . 4. t sk(0) is the skew between outputs when they are selected for 0t u . 5. t skewb is the skew between outputs (xnq0 and xnq1) from a and b banks when they are selected for 0t u. 6. there are 3 classes of outputs: nominal (multiple of t u delay), inverted (x4q0 and x4q1 only with x4f0 = x4f1 = high), and divided (x3q1:0 and x4q1:0 only in divide- by-2 or divide-by-4 mode). test condition: xnf0:1=mm is set on unused outputs. 7. t dev is the output-to-output skew between any two devices operating under the same conditions (v ddq , v dd , ambient temperature, air flow, etc.) 8. t is measured with ref input rise and fall times (from 0.7v to 1.7v) of 0.5ns. measured from 1.25v on ref to 1.25v on xfb. 9. measured at 1.7v. 10. measured at 0.7v. 11. t lock is the time that is required before synchronization is achieved. this specification is valid only after v dd /v ddq is stable and within normal operating limits. this parameter is measured from the application of a new signal or frequency at ref or xfb until t pd is within specified limits. 12. lock detector may be unreliable for input frequencies less than approximately 4mhz, or for input signals which contain signi ficant jitter.
9 industrial temperature range idt5t9955 2.5v programmable skew dual pll clock driver turboclock w 1.7v t pwl t pwh t orise t ofall 0.7v 1ns 1ns 1.7v 0.7v 2.5v 0v v th = 1.25v 150 ? v ddq output 150 ? 20pf output 20pf for lock output for all other outputs v th = 1.25v ac test loads and waveforms lvttl input test waveform 2.5v output waveform
10 industrial temperature range idt5t9955 2.5v programmable skew dual pll clock driver turboclock w ref fb q other q inverted q ref divided by 2 ref divided by 4 t ref t skew2 t skew3, 4 t skew1, 3, 4 t skew2, 4 t skew3, 4 t skew3, 4 t skew2 t skewpr, b t skew0, 1 t ccj1-3, 4-6, 8-12 t odcv t odcv t rpwh t rpwl t skewpr, b t skew0, 1 t ( ) ac timing diagram notes: pe: the ac timing diagram applies to pe=v dd . for pe=gnd, the negative edge of fb aligns with the negative edge of ref, divided outputs change on the negative edge of ref, and the positive edges of the divide-by-2 and the divide-by-4 signals align. skew: the time between the earliest and the latest output transition among all outputs for which the same t u delay has been selected when all are loaded with 20pf and terminated with 75 ? to v ddq /2. t skewpr : the skew between a pair of outputs (xnq 0 and xnq 1 ) when all eight outputs are selected for 0t u . t skewb : the skew between outputs (xnq 0 and xnq 1 ) from a and b banks when they are selected for 0t u . t skew0 : the skew between outputs when they are selected for 0t u . t dev : the output-to-output skew between any two devices operating under the same conditions (v ddq , v dd , ambient temperature, air flow, etc.) t odcv : the deviation of the output from a 50% duty cycle. output pulse width variations are included in t skew2 and t skew4 specifications. t pwh is measured at 1.7v. t pwl is measured at 0.7v. t orise and t ofall are measured between 0.7v and 1.7v. t lock : the time that is required before synchronization is achieved. this specification is valid only after v dd /v ddq is stable and within normal operating limits. this parameter is measured from the application of a new signal or frequency at ref or fb until t pd is within specified limits.
11 industrial temperature range idt5t9955 2.5v programmable skew dual pll clock driver turboclock w ordering information package x -40c to +85c (industrial) i idt xxxxx xx package device type 5t9955 2.5v programmable skew dual pll clock driver turboclock w fine pitch ball grid array bf corporate headquarters for sales: for tech support: 2975 stender way 800-345-7015 or 408-727-6116 logichelp@idt.com santa clara, ca 95054 fax: 408-492-8674 (408) 654-6459 www.idt.com

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